Data converters are an essential element of the signal processing chain in today's system-on-a-chip (SoC) applications such as high-data-rate telecom systems or high-quality audio and video equipment. The sampling clock's quality is the key factor of the systems performance incorporating data converters. Uncertainty of the time instant (defined as a clock jitter) when the analog-to-digital converter (ADC) samples the signal increases noise, which degrades the overall system performance. The higher clock jitters, the lower SNR the signal processing system obtains. The theoretical maximum SNR imposed on ADC performance as a result of a specified sampling clock jitter can be described as the following equation:
  SNR  =      20    ⁢                  ⁢          log      ⁡              [                  1                      2            ⁢                                                  ⁢            fin            ⁢                                                  ⁢                          T              j                                      ]            fin is the input signal frequencyTj is the clock jitter
FIG. 1 illustrates a block diagram of today's typical system-on-a-chip (SoC) integrated circuit. A pair of differential clocks CKP/CKN is fed into SoC from a clock source externally. The signal amplitude of the input clock sources is usually quite small in order to achieve good linearity. A buffer is required to amplify the clock signal amplitude to a full rail-to-rail swing and also drive the large capacitance due the long routing path from the buffer to ADC or DAC. The clock needs to maintain specified characteristics such as low noise, low jitter, high common mode rejection and supply rejection during the amplification, otherwise ADC/DAC performance may be limited by the deteriorated clock.
Another important aspect of the clock is the duty cycle, which determines the time of active high and active low during one clock cycle. FIG. 2 shows a four-stage Pipelined ADC block diagram. Each stage either is executing sample function or gain function. The even stage and odd stages are alternating sample and gain function in order to gain data throughput. When the odd stages are performing sample function, the even stages are undertaking gain function. The active high time of clock is used for odd stages to perform sample function whereas the active low time is used for even stages to perform sample function. The duty cycle change the active time and affect data converter performance. For example, pipelined ADC linearity is often limited by the settling time of the first stage during gain function. Adjusting the duty cycle can obtain more time for first stage settling and improve linearity and associated performance.